bist中文是什么意思

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中文翻译
造句

阿拉伯学者
内建自
内装自测试

bist built in self test 内置自测试
bist built-in self test 内建的自测试
bist,built-in self test 内建的自测试
built-in self test (bist) 内置自测试
wo bist du jetzt 你现在在哪
bissy 比西; 你对
bissuti 比萨蒂细平布
bissubstitution 双取代作用
bista 比斯塔
bissot 比索
bista deepak 比斯塔
bissora 比索朗

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例句与用法

3 zorian y . a distributed bist control scheme for complex vlsi devices . in proc . ieee vlsi test symposium vts 93 , atlantic city , nj , 1993 , pp . 4 - 9
在混合bist方案中，我们会在伪随机测试过程中终止伪随机测试，因为剩下的伪随机测试会降低伪随机测试的故障覆盖率。
Then , the thesis , based on march c - algorithm , shadow read and shadow write technologies , put forwards bist arithmetic for the 20 - port register file
之后本文在marchc -算法的基础上,结合shadowread和shadowwrite技术,首次提出了针对20端口寄存器文件的bist算法。
The design is simulated by hspice , star _ sim and star _ simxt under different condition and the results are given . the dft to sram is discussed and bist and bisr circuit are designed
设计用hspice 、 star _ sim 、以及star _ simxt进行仿真，并对不同仿真条件下的仿真结果进行了描述。
It discusses the architecture of testbench in functional verification of dtv chip and detailed accounts realization of memory bist ( build in self test ) method
本章介绍了各种主流验证测试方法，着重叙述了dtv芯片中功能验证的平台结构设计和存储器内建式自测试( bist )的具体实现。
In proc . ieee international workshop on memory technology , design and test , san jose , ca , usa , august 1997 , pp . 79 - 86 . 8 renovell m . sram - based fpgas : a structural test approach
对于le非lut部分的测试来说，我们有一个类似于上述第三类的方案，其中bist测试fpga的le ，而这些le组成了tpg且cut进行了交换。
We assume a hybrid bist approach , where a test set is assembled , for each core , from pseudorandom test patterns that are generated online , and deterministic test patterns that are generated off - line and stored in the system
在混合的bist方法中，对于每个芯核的测试向量集由在线产生的伪随机测试向量以及离线产生并且存储于芯片上的确定型向量组成。
Since the chip has interior sram and it ' s difficult and slow to test sram exteriorly , in chapter four we use the technique of bist in design of testability of sram , which makes it possible to test the memory at normal working speed
由于片内有sram ，而sram的片外测试比较困难且速度较慢，所以文中第四章采用bist技术对sram进行了可测性设计，完成后可以用正常的工作速度对存储器进行测试。
In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system , consisting of multiple cores , under given memory constraints , so that the total test time is minimized
与此同时为了减少测试成本以及产品上市时间，测试时间必须被最小化。在混合的bist方法中，伪随机向量的长度是决定整个测试过程的行为的一个重要参数。
Bist is an efficient solution for the testing of soc . it is built up with prompting and responding circuits and these two parts are added to the circuit being tested so that the engineer need not consider the testing vector , for it ' s generated automatically
而内嵌自测试技术对于解决soc生产测试的问题非常有效，它将一个激励电路和响应电路中加到被测电路中，从而使测试人员不必再考虑测试向量的问题，因为它是自动生成的。
In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ) . processor and uart ( universal asynchronous receiver transmitter ) , these cores are used in this dissertation , fpu is used for floating point complex fft processor , uart is used for fft processor " s peripheral and our test platform . in chapter 6 we discuss the design for testability , including atpg , bist and jtag method , discuss the different verification and simulation strategy in soc scale facing to different modules , build up the test platform which is used to test high performance application specified digital signal processing processor . in chapter 7 we summarize the research results and creative points , and point out the further work need to do in the future
第五章提出了基于ieee754浮点标准的浮点运算处理器的设计和异步串行通信核的设一浙江大学博士学位论文计，提出了适合硬件实现的浮点乘除法、加减运算的结构，浮点运算处理器主要用于高速fft浮点处理功能，异步串行通信核主要用于pft处理器ip核的外围扩展模块以及本文所做的验证测试平台中的数据接口部分第六章提出了面向系统级芯片的可测试性设计包括了基于扫描测试atpg 、内建自测试bist 、边界扫描测试jtag设计，在讨论可测试性设计策略选择的问题上，提出了针对不同模块进行的分别测试策略，提出了层次化jtag测试方法和扫描总线法，提出了基于fpga