parallel architectures中文是什么意思

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中文翻译
造句

平行架构，併列架构

computer architectures 计算机体系结构
details in architectures 建筑细部
basic computer architectures 基本计算机体系结构
corporate advanced system architectures 公司先进系统结构
drive array architectures 磁盘机阵列体系结构
qos network architectures 服务质量网络结构
be parallel to 和……平行，和……一样; 平行于; 与...平行, 与...类似
be parallel with 与...同时, 随着..., 与...比较, 与...相应, 与...并联
in parallel 并联的; 开联
in parallel with 与...平行, 与...同时, 与...并联
in-parallel 并联平行
parallel adj. 1.平行的；并行的 (to; with); 【电学】并联的。 2.同一方向的，同一目的的。 3.相同的，同样的，相似的，对应的。 a parallel instance [case] 同样的例子[情况]。 His prudence is parallel to his zeal. 他固然谨慎，也同样热心。 run parallel with 和…平行。 n. 1.平行线[面]。 2.相似，类似；相似物，相当的人[物]。 3.比较，对比。 4.纬度圈，纬线。 5.【军事】平行堑壕。 6.【印刷】平行号〔‖〕。 7.【电学】并联。 the parallel of altitude [declination, latitude] 平纬[赤纬，黄纬]圈。 draw a parallel between ... 在…之间作对比。 in parallel with 和…并行，和…对应。 without (a) parallel 无与匹敌的。 vt. (-l(l)-) 1.使成平行；与…平行。 2.与…相匹[配得上，相应]。 3.对比，比较… (with)。 n. -ism 【计算机】并行计算。
parallel in 并联输入; 并网; 并行输入
parallel to 平行的，并列的；相同的，类似的; 平行于; 同...平行; 与……平等,类似
parallel with 与...比较
parallel-in 并行输入
parallel…with 把……与……比较
in series and parallel; series-parallel 串并联；混联
parallel parallel operation 并行并行运算
parallel-parallel logic 并并行逻辑; 并行-并行逻辑
- parallel universes 平行宇宙
aautomatic parallel 自动平行
absurd parallel 荒唐的比拟
access, parallel 并行存取
adjustable parallel 活动平(行)垫片, 可调(整)平(行)垫铁; 活动平垫铁; 活动平行垫片

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例句与用法

The distributed networked parallel architecture and load balance resolution scheme which is adapt to this kind of architecture have been simulated on the surface vessel command and control system artificial platform, and the experiment shows that the performance of the surface vessel command and control system is higher than that of the original distributed system by making use of this kind of method and proves that the method discussed in this thesis has some practical value
本文所提出的分布式网络并行体系结构和适应于这种体系结构的负载平衡方法在舰载指控系统仿真平台上做了仿真试验，证明这种方法的应用使舰载指控系统在性能上比原有的分布式系统有所提高，从而验证了本文所提出的方法具有一定的实用价值。
In general, fpga is mostly used in high-speed communications systems or high-speed signal processing systems because of its high-speedly and parallel architecture . however, in this thesis, it was applied to a low-speed and low power consumption system-a underwater long-range remote control reception system to realize decoding of remote control instructions in the frequency domain, and made the satisfactory result
一般来讲，fpga多用于高速通信和高速信号处理领域，以发挥其处理速度快的特点，本文将其应用于一低速低功耗系统??某水下远程遥控接收系统，主要用其在频域来实现水下远程遥控的解码，取得了令人满意的效果。
Check the current and voltage on charge or discharge, use fuzzy control principle and ah approach to estimate the soc, and correct the actual charge to get the exact result, in this work, a multi-layer feed forward neural paradigm is used for soc fuzzy estimator design, and a rapid learning algorithm that is realized model structure identification is proposed also, and find the fuzzy principles make use of their massively parallel architecture and learning capacity
构造一多层前馈神经网络来进行模糊推理，提出了一种快速学习算法用于网络的学习过程，利用神经网络的并行计算、自学习的特性，根据样本数据发现模糊推理规则，并在应用过程中对模糊规则自动修正，提高预测准确性。这种方法不需要对蓄电池有很多的先验知识，不需要建立复杂的数学模型。
Parallel machine tool is the outcome of parallel architecture and nc machine tool . compared with traditional machine tool, parallel machine tool has such advantages as better stiffness, high load carrying capacity, precise positioning capability and high respond velocity, so it has greatly wide application foreground
并联机床是并联机构与数控机床两个概念相结合的产物，并联机床与传统机床相比具有刚度大、承载能力强、位置精度高、响应速度快等许多优点，其应用前景十分广阔。
Three decoder architectures, parallel, serial and partially-parallel approaches, are analyzed in this thesis . a kind of novel partially-parallel architecture for decoding ldpc code is proposed . the trade-off between the performance of the decoder, hardware complexity and data throughout can be achieved with this partially-parallel architecture for the random parity check matrix
论文分析了三种不同的译码器结构:并行结构、串行结构以及部分并行结构,并提出了一种新颖的部分并行结构的ldpc译码器,较好地解决了当校验矩阵为随机结构时,译码性能、硬件资源和数据吞吐量平衡的问题。
Three decoder architectures, parallel, serial and partially-parallel approaches, are analyzed in this thesis . a kind of novel partially-parallel architecture for decoding ldpc code is proposed . the trade-off between the performance of the decoder, hardware complexity and data throughout can be achieved with this partially-parallel architecture for the random parity check matrix
论文分析了三种不同的译码器结构:并行结构、串行结构以及部分并行结构,并提出了一种新颖的部分并行结构的ldpc译码器,较好地解决了当校验矩阵为随机结构时,译码性能、硬件资源和数据吞吐量平衡的问题。

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Last modified time:Fri, 15 Aug 2025 00:29:56 GMT