programmable gate array中文是什么意思

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中文翻译
造句

可编程序门阵列

gate gate2 n. 1.〔古语〕街道，路〔一般 ...
array vt. 1.打扮，装饰。 2.使…列队，排列。 3.提出 ...
array programmable gate 可编程门阵列
array, programmable gate (pga) 可编程门阵列
field programmable gate array 可现场编程门阵列; 现场可编程逻辑阵列
filed programmable gate array 现场可程式闸门阵列
pga programmable gate array 可编程门阵列
programmable gate array (pga) 可编程门阵列
antifuse field programmable gate array 反熔丝可现场编程门阵列
array, antifuse field programmable gate 反熔丝可现场编程门阵列
array, field programmable gate (fpga) 可现场编程门阵列
field programmable gate array, fpga 现场可编程门阵列
fpg field programmable gate array 现场可编程
fpga field programmable gate array 现场可编程门阵列
mpga mask programmable gate array 掩模可编程门阵列
programmable array 可编程序阵列
programmable gate 程序可控门; 程序控制门
array, gate 门阵列
gate array 门数组; 门阵列; 栅阵列
array programmable logic 可编程逻辑阵列
array, programmable logic (pla) 可编程逻辑阵列
field programmable logic array 现场编程逻辑阵列; 现场可编程序的逻辑阵列; 现场可编程序逻辑阵列
field-programmable logic array 场程序逻辑阵列; 场致程序逻辑阵列
fuse programmable array logic 熔丝烧断可编程序逻辑阵列
logic multiple array programmable 多重阵列可编程逻辑

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例句与用法

Fpga ( field programmable gate arrays ) is a new type of ic ( integrated circuit ) in recent years . it has advantages of compactness 、 economy 、 high speed 、 low consumption 、 full integration and good applicability . it is easy to be developed and be maintained
现场可编程门阵列器件( fieldprogrammablegatearrays )是近年来崭露头角的一类新型集成电路,它具有简洁、经济、高速度、低功耗等优势,又具有全集成化、适用性强,便于开发和维护(升级)等显著优点。
In view of numerous digital and analog signals need to be processed , and the difficulty of real - time processing of multi channel 400 hz ac signal , vhdl ( vhsic hardware description language ) is applied to design the digital circuit , which is successfully realized in field programmable gates array ic - xc2s100
针对i o模块中需要处理的数字量和模拟量较多的事实，以及多路400hz信号的实时处理较为繁重的现状，作者采用了现场可编程门阵列( fpga )加以解决。
After the investigation of the general technology of hardware implementation , how to implement the kasumi algorithm using field programmable gate array ( fpga ) device is discussed in detail , and the author develops the cipher chip of kasumi algorithm , the kasumi cipher card based on 32 - bits pci bus , the wdm device driver that used in windows2000 / xp , and the software to demostrate encrypting data link . finally , an application demostration is constructed with all the above implementation
在此硬件实现的结果芯片基础上，设计了32位的基于pci总线的kasumi加密卡，编写了windows2000 xp下的windows驱动程序模型( wdm )驱动程序和链路加密应用程序，由此构成一个应用演示系统，作为研制结果的应用评估，为进一步进行第三代移动通信系统相关安全技术研究和开发提供了基础条件。
Because period narrow band signals are the main part of background noises , this thesis uses hardware description language to design a multi - band finite impulse response filter ( fir ) and downloads the program into filed programmable gate array to eliminate the period narrow - band interferences in the background noises
3 )在现场环境中，背景干扰主要是周期性的窄带，本文利用硬件描述语言( vhdl )设计了一个多带fir有限冲击响应滤波器。应用到可编程逻辑器件中，消除了背景噪声中的周期性干扰，为信号的进一步处理提供尽可能干净的信号。
Finally , on the basis of the mpeg - 1 layer hencoding hardware structure , the block of logic communicates with the pc over the parallel port and the interface for flash memory are design . then a mpeg audio coding system , which applies to store audio signal , is presented through the field programmable gate array device technology
最后，在mpeg - 1层编码的硬件结构的基础上，结合计算机并口通信和flash存储器的接口模块，采用现场可编程逻辑器件fpga技术，最终设计了一种应用于音频信号存储的mpeg音频编码系统。
With the development of electronic and eda ( electronic design automatic ) technology , large scale integration can be replaced by pld ( programmable logic device ) and fpga ( field programmable gates array , which can realize the function of the programmable interface chip and many different programmable interface chips
随着电子技术和eda技术的发展，大规模可编程逻辑器件pld ( programmablelogicdevice ) 、现场可编程门阵列fpga ( fieldprogrammablegatesarray )完全可以取代大规模集成电路芯片，实现计算机可编程接口芯片的功能，并可将若干接口电路的功能集成到一片pld或fpga中。
With rapid developments of system on chip ( soc ) , programmable logic devices ( pld ) , including complex programmable logic device ( cpld ) and field programmable gate array ( fpga ) , can support in - system programmability ( isp ) and become more popular in the world . this requires better download cables than before , which are used to program plds
随着片上系统( soc , systemonchip )时代的到来,包括复杂可编程逻辑器件( cpld , complexprogrammablelogicdevice )和现场可编程门阵列( fpga , fieldprogrammablegatearray )的可编程逻辑器件,具有系统内可再编程的独特优点,应用越来越广泛。
In order to meet the requirement of real time of system , modularization configuration and dsp + fpga is used for realizing parallel processing of signal in system hardware . the implementation of fft algorithms is performed by field programmable gate arrays ( fpga ) , and spectrum analysis is done by dsp , and at the same time , sequence control of entire system is performed by cpld
为满足系统实时性要求,系统硬件电路采用模块化结构,利用快速的dsp + fpga实现信号的并行处理,采用fpga实现fft算法,使用dsp完成谱信号的分析,同时通过cpld来完成整个系统时序的控制。
The design of hardware is based on fpga ( filled programmable gate array ) and mcu ( micro computer unit ) , providing small volume , reliability and simply control . the design of software is based on keil c51 and foundation 3 . 1 . it can realize many complex functions , so the flexibility of application is greatly strengthened
数据采集卡的硬件设计基于现场可编程门阵列（ fpga ）和单片机（ mcu ），体积小、工作可靠、控制简单、外围电路少；软件设计采用keilc51和foundation3 . 1 ，可根据用户需要实现多种复杂的功能，极大的提高了应用的灵活性。
In this dissertation , the method to design and realize the digital receiver in the field programmable gate array ( fpga ) has been discussed ; combining coordinate rotation digital compute ( cordic ) to design nco , we get a efficient structure without multiplications
本论文正是运用现场可编成逻辑器件( fpga )设计与实现数字接收机问题开展研究,结合坐标旋转数值计算( cordic )算法实现数控振荡器( nco ) ,得到一种免乘法器高效可移植性好的数字接收机fpga实现结构,并在现有的硬件平台上进行了接收机系统的调试,测试结果表明该接收机能够达到系统指标要求。

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Last modified time:Sun, 17 Aug 2025 00:29:56 GMT