parallel adj. 1.平行的;并行的 (to; with); 【电学】并联的。 2.同一方向的,同一目的的。 3.相同的,同样的,相似的,对应的。 a parallel instance [case] 同样的例子[情况]。 His prudence is parallel to his zeal. 他固然谨慎,也同样热心。 run parallel with 和…平行。 n. 1.平行线[面]。 2.相似,类似;相似物,相当的人[物]。 3.比较,对比。 4.纬度圈,纬线。 5.【军事】平行堑壕。 6.【印刷】平行号 〔‖〕。 7.【电学】并联。 the parallel of altitude [declination, latitude] 平纬[赤纬,黄纬]圈。 draw a parallel between ... 在…之间作对比。 in parallel with 和…并行,和…对应。 without (a) parallel 无与匹敌的。 vt. (-l(l)-) 1.使成平行;与…平行。 2.与…相匹[配得上,相应]。 3.对比,比较… (with)。 n. -ism 【计算机】并行计算。
An interface unit or circuitry that converts data to and from the representation used by a particular peripheral device or class of peripheral devices ; for example , a device that converts between bit serial and bit parallel and resolves differences in transmission speeds 一种接口部件或电路,用来把数据转换成某种特殊的外围设备上的表示或某类外围设备上的表示或把此种表示转换成数据。例如,一台在串行位和并行位之间作转换且解决传输速度差别的设备。
8051 processor testing system was designed to test the sample in 16 bits parallel interface . because of the limitation of the testing system interface , however , easyarm2131 based on arm7tdmi - s was selected to use in 18 bits parallel interface test . and it sufficed the higher bits parallel interface test such as 18 bits , 24 bits , or more , while 8051 testing system ca n ' t do 为测试16bit并行接口,设计了以8051芯片为处理器的测试机;在测试18bit并行接口时,由于8051测试机的接口限制,采用了基于arm7tdmi - s核的easyarm2131开发板系统,解决了8051无法满足18bit乃至以后可能用到的24bit甚至更高的并行接口问题。
This card largely depends on three integrate chips to fulfill its function : 1 ) nic control main chip , corresponding the mac sublayer of ethernet , to realize csma / cd media access protocol , manage the sending and receiving buffers integrated on the chip and provide motherboard pci interface . 2 ) serdes ( serializing and deserializing ) chip , corresponding pcs and pma sublayers in ethernet , mainly to complete 8b / 10b coding and convert 10 bits parallel data to serial data , and convert them again at the receiving end . 3 ) fibre transceiver unit , completing light - electrical conversion of seri 该网卡主要由3块集成的芯片完成其功能,分别是i )网络控制主芯片,对应于以太网的mac子层,主要完成csmaicd介质访问协议,管理片上集成的发送和接收缓冲区,并提供和主板p0总线的接口: b ) s rd s (串行解串行化器)芯片,对应于以太同的pcs和pma子层,主要完成sb lob编码并将10位并行的数据转换为串行数据,在接收端完成相反的功能:涌)光纤收发器,完成串行数据的光电转换功能。